Surface Code Logical Error Rate Calculator
The planar surface code is a leading candidate for fault-tolerant quantum computation because it combines a high threshold with a simple 2D nearest-neighbor layout. It encodes quantum information into a larger patch of physical qubits and uses repeated stabilizer measurements to detect and correct local errors without directly measuring (and collapsing) the logical state. The key design dial is the code distance d: roughly speaking, it is the minimum number of physical errors required to create an undetectable error chain that implements a logical fault. When the physical error rate is below a threshold, increasing d suppresses logical errors approximately exponentially.
What this calculator computes
- Estimated logical error rate per round (or per “effective cycle”), using a common empirical scaling law for the surface code.
- Below-threshold check: whether the entered physical error rate p is less than the assumed threshold pth.
- Rough qubit overhead for a planar patch, using the back-of-the-envelope estimate n ≈ 2d2.
- Estimated distance required to meet a target logical error rate, by inverting the same empirical formula (useful for quick sizing).
Symbols and definitions
| Symbol | Meaning | Typical range / notes |
|---|---|---|
| p | Physical error probability (per gate / measurement / round, depending on your modeling) | Often 10−4 to 10−2 in projections; must be < pth for the scaling to be meaningful |
| pth | Threshold physical error rate for the chosen code+decoder+circuit/noise assumptions | Common ballpark: ~0.5%–1% (0.005–0.01), but it varies substantially |
| d | Code distance (minimum length of a nontrivial logical operator) | Integer, typically odd in many planar layouts (but the scaling is often used for any integer) |
| pL | Logical error rate (probability of a logical fault per effective round) | Decreases rapidly with increasing d when p < pth |
| n | Approximate physical qubit count for one planar logical qubit | Here estimated as n ≈ 2d2 (very rough) |
Formulas used
A widely used empirical approximation for the planar surface code logical error rate (in the below-threshold regime) is:
Interpretation:
- The ratio p/pth measures how far below threshold you are.
- The exponent ( d+1 )/2 makes the dependence on distance close to exponential in d.
- The prefactor 0.1 is not universal; it is a convenient fit to certain simulation/decoder settings.
For qubit overhead, the calculator uses a common “rule of thumb” for a planar patch that includes data and ancilla qubits:
n ≈ 2d2
If you enter a target logical error rate pL,target, the same empirical law can be inverted to estimate the distance needed (still assuming p < pth):
( d+1 )/2 ≈ log( pL,target/0.1 ) / log( p/pth )
and then d is rounded up to an integer (often you may choose the next odd distance for a standard planar layout).
Interpreting the results
- If p ≥ pth: the below-threshold scaling law is not expected to hold; increasing distance may not reduce logical errors reliably, and the “required distance” estimate can become unstable or misleading.
- If p is comfortably below pth: each increment in distance can reduce pL by a large factor. Small improvements in p can translate into large savings in distance and qubits.
- Overhead estimate (n): treat n ≈ 2d2 as a sizing heuristic. Real devices may require additional routing, leakage mitigation, readout ancillas, lattice surgery boundaries, or multiple patches per logical qubit, all of which increase overhead.
Worked example
Suppose you have:
- Physical error rate: p = 1×10−3
- Threshold: pth = 1×10−2
- Distance: d = 5
Compute the ratio: p/pth = 0.1. The exponent is (5+1)/2 = 3. Then:
pL ≈ 0.1 × (0.1)3 = 0.1 × 0.001 = 1×10−4
Overhead estimate: n ≈ 2d2 = 2×25 = 50 physical qubits for one planar logical qubit (roughly).
If you instead want a target pL,target = 1×10−6 at the same p and pth, solve:
0.1×(0.1)(d+1)/2 = 1×10−6 ⇒ (0.1)(d+1)/2 = 1×10−5 ⇒ (d+1)/2 = 5 ⇒ d = 9.
Quick comparison table (how distance impacts overhead)
| Distance d | Exponent (d+1)/2 | Estimated qubits n ≈ 2d² | Scaling intuition (for fixed p/pth < 1) |
|---|---|---|---|
| 5 | 3 | 50 | Baseline example distance |
| 7 | 4 | 98 | One more power of (p/pth) suppression |
| 9 | 5 | 162 | Often a big step toward very low logical error |
| 11 | 6 | 242 | Higher reliability, rapidly increasing qubit cost |
Assumptions & limitations
- Empirical model: The relation pL ≈ 0.1( p/pth )(d+1)/2 is a convenient fit inspired by numerical studies. The prefactor (0.1), the effective exponent, and even the functional form can change with the decoder, syndrome-extraction circuit, and noise model.
- Below-threshold regime: The formula is intended for p well below pth. Near or above threshold, logical error rates may stop improving with distance, and “required d” estimates can be meaningless.
- What “p” represents: Hardware reports multiple error channels (1-qubit gates, 2-qubit gates, measurement, idle, crosstalk, leakage). Collapsing these into a single scalar p is an approximation; a more faithful model uses circuit-level noise and simulates the full syndrome extraction.
- Time vs. rounds: Logical error rates can be quoted per round, per code cycle, per unit time, or per logical gate. This calculator does not convert between those; you must align the meaning of p with your intended “per-round” interpretation.
- Overhead estimate is coarse: n ≈ 2d2 is a rule of thumb for a single planar logical qubit patch. Real architectures often require extra spacing, boundaries for lattice surgery, ancillas for state injection/distillation, and routing overhead that can dominate total qubits.
- Distance parity/layout details: Some standard planar layouts prefer odd d and have different constants for rotated vs. unrotated patches. Treat the distance estimate as a sizing guide, not a layout guarantee.
Use this tool for fast intuition and back-of-the-envelope planning. For hardware-level predictions, validate with decoder- and circuit-specific simulations under a realistic noise model.