ADC Quantization Noise Calculator

Introduction to ADC quantization noise, SNR and useful resolution

An analog-to-digital converter represents a continuously variable input with a finite set of digital output codes. The difference between the input voltage and its represented level is quantization error. When a signal traverses many codes without a repeating clock-synchronous pattern, engineers commonly model that error as uniformly distributed noise. This ADC quantization noise calculator uses that useful ideal model to estimate code width, RMS quantization noise, full-band signal-to-noise ratio, oversampling process gain, required nominal resolution and effective number of bits.

Nominal bit count is not automatically useful resolution. An ideal converter can approach the familiar full-scale-sine benchmark $\mathrm{SNR}=6.02N+1.76$ dB, but a practical converter also has reference noise, thermal noise, distortion, aperture uncertainty, input-driver errors and interference. ENOB translates a measured sine-test SINAD into the number of bits an equivalent ideal converter would provide under that particular test condition. Use this page as a design baseline, then compare the result with measurements made at the intended input frequency, bandwidth, sample rate and temperature.

Oversampling is included because a higher sample rate spreads approximately white quantization noise over a wider Nyquist band. A suitable digital low-pass filter and decimator can discard noise outside the retained band. Sampling faster alone does not improve a result: the filter, useful bandwidth, analog noise floor and possible noise shaping determine the gain that a real system can keep.

How to use the ADC noise, target-SNR and ENOB calculator

Select the calculation mode that matches the information already known. Bit-depth mode starts with a whole-number converter resolution and reports its LSB weight, RMS quantization noise and ideal SNR. Target-SNR mode starts with an in-band requirement, removes ideal oversampling gain, and rounds the required physical converter size upward. Measured-SINAD mode starts with a trusted FFT or data-sheet number and a test-tone level in dBFS to estimate ENOB.

Enter the complete ADC input span as full-scale range. A bipolar ±5 V input spans 10 V, while a 0 V to 3.3 V input spans 3.3 V. The oversampling ratio is $\mathrm{OSR}=\frac{f_s}{2\mathrm{BW}}$, where $f_s$ is sample rate and $\mathrm{BW}$ is retained one-sided bandwidth. Use OSR 1 when the complete Nyquist band remains. For a SINAD test, 0 dBFS means the stated full-scale sine reference and backed-off tones use negative values.

After computing, read the result summary first, then inspect the nearby-bit table. One extra bit halves the LSB and the RMS quantization-noise voltage, while increasing ideal wideband SNR by about 6.02 dB. The plotted waveform is a reminder that a quantizer produces a staircase approximation; it is not a promise of absolute DC accuracy, linearity or freedom from distortion.

Formulas for ADC LSB size, quantization noise and ideal SNR

An $n$-bit ADC divides its full-scale range into $2^n$ nominal bins. The code count and code width are therefore:

The calculator also calls this code width $q$. Under the ordinary uniform-error assumption, the error has equal probability between the two half-LSB limits, has mean zero, and has the following variance:

The standard SNR derivation uses a sine wave whose peak-to-peak amplitude fills the input range. Its RMS voltage is:

Dividing the sine RMS voltage by quantization-noise RMS gives the ideal relation. The voltage range cancels, so range changes noise in volts but not ideal SNR in dB.

This benchmark integrates noise from DC to $f_s/2$. It assumes an ideal transfer curve, no missing codes and noise-like error between $-\frac{q}{2}$ and $\frac{q}{2}$. Quiet DC levels and coherent tones can create patterned error or discrete spurs instead.

Endpoint conventions explain some data-sheet wording. A useful straight-binary reconstruction model is:

The top code is one less than the code count, but that endpoint detail does not change the engineering LSB definition used here. Offset binary and two’s-complement coding change bit interpretation, not bin count or ideal quantization-noise magnitude.

Oversampling process gain, sample rate and retained bandwidth

With white quantization noise and an effective low-pass decimation filter, keeping a smaller output bandwidth improves in-band SNR:

Every OSR doubling adds $10{\log }_{10}2=3.01$ dB, or half an ideal bit. Gaining $\beta$ bits needs $4^{\beta }$ times OSR. The equivalent in-band resolution and the planning definitions are:

For example, 20 kHz retained bandwidth at OSR 32 requires at least 1.28 MSPS in this one-sided low-pass convention. Practical systems often sample faster to leave analog-filter transition width and obtain stronger digital stop-band attenuation. A decimation ratio D and OSR are related but need not be identical. Oversampling raises interface traffic, memory use, filter latency and power, so it matters only when the analog noise floor leaves quantization noise worth reducing.

SINAD-based ENOB, tone backoff and full-scale conventions

SNR normally excludes harmonics, while SINAD includes both noise and distortion. Conventional effective number of bits therefore comes from SINAD:

If the sine test tone is below full scale, correct the amplitude before interpreting ENOB:

Because this form accepts dBFS, a −6 dBFS tone receives a +6 dB correction. Its RMS voltage and uncorrected ideal SNR follow:

Check the manufacturer’s convention carefully. dBFS is relative to a stated converter full-scale reference, dBc is relative to the applied carrier, and dBm is power relative to 1 mW in a stated impedance. ENOB is conditional on input frequency, sample rate, reference drive, FFT bandwidth, distortion treatment and temperature; it is not a universal part-number property.

Practical ADC noise limits beyond the ideal quantizer

A complete input-referred ADC noise budget combines independent RMS sources by root-sum-square after every value is referred to the same input point and bandwidth:

If other circuitry already exceeds the noise limit, extra nominal ADC bits cannot fix the system. Thermal noise is one common lower bound:

Noise density must be integrated through the actual analog and digital transfer functions. Wideband amplifier and reference noise can alias into band when the analog filter is inadequate. Reference settling, source resistance, switched-capacitor charge kickback, gain setting and supply coupling often explain a measured result that is much worse than the q divided by root 12 prediction.

At high input frequencies, clock jitter can set a stricter ceiling:

Jitter includes clock-source, distribution and ADC-aperture contributions. At the input, a SAR converter must also settle during acquisition. A first-order illustration is:

Dither can make repeated quantization patterns more noise-like, but it adds RMS noise. Independent dither and averaging behave as follows:

The square-root-M benefit requires independent noise. It does not remove drift, periodic interference, correlated quantization spurs or clock-related distortion. Sigma-delta converters additionally use noise shaping, so their published output-rate and digital-filter noise specifications are usually better guides than a flat-noise OSR estimate alone.

Worked example: a 12-bit ADC across a 5 V range

Consider a 12-bit converter spanning 5 V, sampled at 1.28 MSPS and digitally filtered to 10 kHz. The OSR is $1.28\times {10}^6/(2\times 10000)=64$. Its code width is $q=5.000/2^{12}=5.000/4096=1.2207$ mV, and its ideal RMS quantization noise is $1.2207\text{mV}/\sqrt{12}=352.4$ µV.

The full-scale sine is $(5.000/2)/\sqrt{2}=1.7678$ V RMS. Its ideal wideband SNR is $20{\log }_{10}(1.7678/352.4\text{µV})=74.01$ dB, matching $6.02\times 12+1.76$. OSR 64 adds $10{\log }_{10}\left(64\right)=18.06$ dB, for an ideal 92.07 dB in band, or $(92.07-1.76)/6.02=15.00$ equivalent bits.

If an FFT instead reports 70.1 dB SINAD at −0.5 dBFS, the corrected ENOB is $(70.1-1.76+0.5)/6.02=11.43$ bits. The shortfall from 12 nominal bits represents combined noise and distortion, not merely quantization. The 18.06 dB process gain remains an ideal prediction and is reduced whenever analog noise or imperfect filtering dominates the retained bandwidth.

Limitations of the ideal ADC quantization model and common questions

The relation $q^2/12$ assumes error distributed across $\pm q/2$. It does not predict reference noise, amplifier noise, DNL, INL, clipping, jitter, settling error or interference. Displayed in-band equivalent bits can exceed nominal resolution under a white-noise filtering model; that describes lower RMS uncertainty in a narrower bandwidth, not extra instantaneous codes or guaranteed absolute accuracy.

Always confirm that the entered full-scale value is the total span, that SINAD and dBFS came from the same measurement convention, and that OSR uses retained one-sided bandwidth. For DC systems, translate input-referred voltage noise through sensor sensitivity and analog gain. For audio, communications and control systems, also account for crest factor, distortion, latency, channel switching, alias rejection and the application’s allowable error. A measurement plan should state bandwidth, window, coherent sampling conditions and whether harmonic bins count as noise.